Automatic Synthesis of Pipeline Structures with Variable Dat Initiation Intervals

In this paper, we propose a novel algorithm for synthesizing the pipeline structures with variable data initiation intervals (DIIs). Compared to previous researches where the pipeline synthesis is confined to those with fixed DIIs, the proposed algorithm tries to optimize the pipeline latency by fully utilizing hardware resources to which abstract operations in high-level design descriptions are assigned. supported in those systems is confined to the pipeline structures with fixed DII (Data Initiation Interval). Pipeline structures with fixed DII have been widely employed for their simplicity of control and design. Pipeline structures with variable DIIs are the generalized form. It is well known that the high throughput can be obtained with variable DIIs. However, the complexity of the synthesis algorithm and pipeline control prevent the pipeline structures with variable DIIs from being utilized in digital system design. By automating the design of pipeline structures with variable DIIs, we can obtain hardware designs with higherperformance in throughput. In this paper, we propose novel algorithms for synthesizing the pipeline structures with variable DIIs. In Section 2, pipelining concepts are described. Scheduling, module allocation for pipeline structures with variable DIIs are presented in Section 3. Section 4 presents the experimental results for benchmarks and conclusions are drawn in Section 5. Determining time-overlapping of pipeline stages, the proposed algorithm performs scheduling and module allocation using the time-overlapping information for the proper control of pipelines with variable DIIs. Experimental results on benchmarks show that significant improvement can be achieved both in speed and in area.